DesignClock (imaFlex CXP-12 Quad and imaFlex CXP-12 Penta platforms)
Type
static read parameter
Default
312.5
Range
[312.5; 400.0]
The parameter represents the design system clock frequency in Mega Hertz.
You can alter the design system clock frequency in VisualApplets, menu
Design, menu item Change FPGA
Clock. Using higher frequency settings as 135 MHz may result
in a timing violation. In this case, reduce frequency.
Availability
imaFlex CXP-12 Quad, imaFlex CXP-12 Penta
DesignClock (mE5 platforms and LightBridge VCL)
Type
static read parameter
Default
125
Range
[125;312.5]
The parameter represents the design system clock frequency in Mega Hertz.
You can alter the design system clock frequency in VisualApplets, menu
Design, menu item Change FPGA
Clock. Using higher frequency settings as 135 MHz may result
in a timing violation. In this case, reduce frequency.
The parameter PcieInterfaceType allows you to select the PCIe interface
type and thus the supported DMA bandwidth.
Generation_2 (default) stands for the PCIe Generation 2 protocol and
provides a bandwidth of 3,600,000 bytes/s.
Generation_1 stands for PCIe Generation 1 protocol and provides a
bandwidth of 1,800,000 bytes/s.
Generation_1 designs utilize slightly less FPGA resources. It is much
easier to achieve timing closure for the applet with a Generation_1 design.
Generation_2 provides maximal performance, but makes it more challenging to
achieve timing closure for the applet. Multiple place and route synthesis runs
will probably be necessary to meet the timing.
Availability
mE5 ironman VD8-PoCL, mE5 ironman VQ8-CXP6D, and mE5 ironman
VQ8-CXP6B
PcieInterfaceType (marathon and LightBridge platforms)
Type
static write parameter
Default
Generation_2
Range
{Generation_1, Generation_2}
The parameter PcieInterfaceType allows you to select the PCIe interface
type and thus the supported DMA bandwidth.
Generation_1: The applet only supports PCIE generation 1. Thus, the
maximum DMA transmission bandwidth is ca. 900 MByte/s (1MByte = 1^10Byte). The
DmaToPC operator is limited so that LinkParallelism x LinkPixelWidth needs to be
<= 64 bit.
Generation_2: The applet supports PCIE generation 2. Thus, the maximum DMA
transmission bandwidth is ca. 1800 MByte/s (1MByte = 1^10Byte). The DmaToPC
operator is limited so that LinkParallelism x LinkPixelWidth needs to be <=
128 bit.
The implementation of Generation_1 consumes less resources than the
implementation of Generation_2. The Generation_1 mode is helpful in designs that
do not need the high bandwidth of Generation_2, but are short of resources.
This parameter allows the user to select the circuitry type for the
external extension GPIO connector. In PushPull mode, the GPIOs are driven
directly.
Parameter Only Affects the GPIO Connector
This parameter has no effect on Front GPIO connector. Only the GPIO
connector is influenced by this parameter.
Availability
imaFlex CXP-12 Quad, imaFlex CXP-12 Penta
GpioType
Type
dynamic write parameter
Default
OpenDrain
Range
{OpenDrain, PushPull}
This parameter allows the user to select the circuitry type for the
external GPIO connector. In PushPull mode, the GPIOs are driven directly.
Parameter Only Affects the GPIO Connector
This parameter has no effect on Front GPIO connector. Only the GPIO
connector is influenced by this parameter.
This parameter is not displayed in the operator's parameter list.
However, the parameter is visible in the runtime environment.
BuildTimeStamp is an automatically generated identification number. It's a
32-bit time stamp that can be read out of the applet during runtime for checking
the consistency between the loaded applet and the loaded applet runtime
environment.
This parameter is not displayed in the operator's parameter list.
However, the parameter is visible in the runtime environment.
32-bit hash over the entry in ProjectName (menu Design, menu item
Properties). This value can be read out of the applet during runtime for
checking the consistency between the loaded applet and the loaded applet runtime
environment.
![[Note]](../common/images/admon/note.png)
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